From 2020-2021 I worked on researching irregular algorithm acceleration using CGRAs. While Barnes-Hut is easily parallelizable, there are interesting methods that can be used to exploit cache locality to further accelerate it. Mapping this algorithm to a CGRA was particularly hard because the tree traversal appears to require a variable state size (ie. a stack or recursive function calls). Since the CGRA has a fixed amount of data that can easily fit into the pipeline, this becomes challenging.

This was my final project for 6.111 that I developed with Cece Chu. As the second FPGA project that I spent a considerable amount of time on, I focused on doing a lot of simulation and testing (as one should with FPGAs). Since our approach to rendering was a little unusual and based on fixed point math, the simulation was critical to validating the concept of the system. All of the simulation was done using verilator to do unit testing, integration testing, and produce simulated renders.

I made this simple audio chat software to play with signal modulation and encoding. The signal is encoded using 4-QAM or 16-QAM and uses matched SRRC filters. The hardest part of the system was the preamble detection used to start and determine the corrections necessary for a signal to be received. The software is also complicated by the fact that it is designed to operate in a chat system and thus does the signal detection and demodulation in real time.

I wrote (and am still working on) this project primarily as a learning experience. If I just wanted a server I would probably (and already have) just wrote the server in javascript on node-js. The use of the sled KV database is nice because it has a good Rust interface and is designed for stateful services, and other embedded database bindings often miss features such as transaction support. Sled, however, isn’t 1.