This was my final project for 6.111 that I developed with Cece Chu. As the second FPGA project that I spent a considerable amount of time on, I focused on doing a lot of simulation and testing (as one should with FPGAs). Since our approach to rendering was a little unusual and based on fixed point math, the simulation was critical to validating the concept of the system.

All of the simulation was done using verilator to do unit testing, integration testing, and produce simulated renders.

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